In large systems, such as computer systems, communication systems, and the like, situations arise where some component (e.g. a memory) of the system is shared by many users or facilities of the system. Such a situation requires an arbitration scheme to decide which facility or user receives preferential access to the shared component. Traditionally, conventional priority arbitration schemes have been implemented by circuitry that is adapted to serially propagate a particular signal to all prospective users. Those users who received the signal early in the propagation chain are afforded the highest priority for gaining access to the system and its components. This conventional priority arbitration technique is acceptable from the standpoint of minimizing the number of circuit lines requires to implement the corresponding arbitration circuitry. However, the conventional priority arbitration technique also has several undesirable characteristics. More particularly, the conventional priority arbitration technique is relatively slow. Moreover, the conventional technique undesirably dictates that priority assignments are fixed according to the layout of the wiring that interconnects the components of the system. As an undesirable result, the location of the system components is also dictated, which would both minimize system flexibility and increase space consumption. What is more, if one system component is removed, some provision must be made to reconnect the otherwise interrupted priority chain.
As a consequence of the undesirable characteristics of the aforementioned technique, another priority arbitration scheme evolved. The corresponding priority arbitration circuitry includes separate request lines that are supplied to each prospective user. The shared component chooses which of the user requests is to be granted. This conventional technique, although relatively fast, is relatively expensive to mechanize. Moreover, numerous signal lines are required, which typically increases the overall size of the corresponding priority arbitration circuitry.
Examples of readily available conventional priority arbitration schemes can be found in the following microelectronic chips manufactured by Texas Instruments Corporation: 4-bit Cascadable Priority Register, types SN54278 or SN74278; and the 8-line-to-3-line Priority Encoder, types SN54LS348 or SN74LS348.